Dipanjan Das with Advisor P. Krein
Power delivery to multi-core processors is becoming increasingly challenging with decreasing transistor sizes and, thereby, their operating voltages. With the increase in number of cores in each processor, the power requirements tend to remain the same with each new generation of microprocessors, and handling transient performance requirements along with efficiency has become much more difficult at lower voltages. Significant improvement in energy efficiency can be achieved by stacking the processor cores in series and regulating the core voltages by differential power processing (DPP). However, for practically achieving higher efficiency than the conventional parallel-connected processor cores, other (software) overheads are required to balance the power consumption of each processor core (such as communication between different voltage domains, scheduling processes to aid voltage balancing, etc.). A tradeoff between these additional overheads and the actual power needed to be processed by the differential power processing converters has to be optimized.
At present, various control schemes for improvement in the dynamics of the differential power processing (DPP) voltage regulator are being developed. One topology suitable for voltage regulation of a series stack of digital loads is the hierarchical element-to-element topology. It has been established that this topology provides improved dynamic performance compared to other non-isolated topologies in regulating stack voltages. Implementation of the bidirectional DPP converters has been one area of focus. A multiphase buck/buck-boost converter with asymmetric current sharing (Figures 26 and 27) was developed for improved efficiency over a wide load range. Improved light-load efficiencies of individual DPP converters is expected to improve system-level efficiencies significantly. An array of CMOS inverters with capacitive loading (for emulating microprocessor load behavior) is currently under development.