PhD student Dipanjan Das with advisor P. Krein
Power delivery to multi-core processors has become increasingly challenging as transistor sizes decrease and, consequently, their operating voltages. With rising core numbers for each processor, the power needs tend to remain the same for each new generation of microprocessors. Handling both transient performance requirements and efficiency has become much more difficult at lower voltages. Significant improvement in energy efficiency can be achieved by stacking the processor cores in series and regulating the core voltages using differential power processing. However, to achieve efficiency higher than the conventional parallel-connected processor cores, other (software) overheads are required to balance the power consumption of each processor core (such as communication between different voltage domains, scheduling processes to aid voltage balancing, etc.). A trade-off must be optimized between these overheads and the actual power required for processing by the differential power processing converters.
Various control schemes are being developed to improve dynamics of the differential power processing voltage regulator. One topology suitable to regulate a series-stack of digital loads is the hierarchical element-to-element topology, which provides improved dynamic performance compared to other non-isolated topologies in regulating stack voltages. This research, supported by the Grainger Center for Electric Machinery and Electromechanics, focuses on implementing individual converters in the topology to maintain high efficiency over a wide output range. A multi-phase buck/buck-boost converter with asymmetric current sharing between phases (Figure 27) and its hardware implementation is being developed.