Dipanjan Das with adviser P. T. Krein
Power delivery to multi-core processors is increasingly challenging as transistor sizes decrease and operating voltages thereby increase. With the growing number of cores in each processor, power requirements tend to remain the same, but handling the transient performance and efficiency requirements has become difficult at lower voltages. Significant improvement in transient performance and energy efficiency can be achieved by stacking the cores in series (thereby increasing the output voltage requirement and relaxing the output impedance requirement for the outer loop converter) and regulating the core voltages by differential power processing (DPP). The load-to-load DPP configuration seems to be most appropriate for our purpose because of its modularity and ease of integration. However for the conventional load-to-load architecture, which comprises back-to-back connected buck-boost converters, the dynamic response is challenging due to the buck-boost nature of the converters. A large number of these converters cannot be connected back to back if the goal is fast transient response. Modified topologies derived from the load-to-load DPP topology are being analyzed. The one shown in Fig. 13 gives better performance in terms of transient response and stability and is effective if a large number of cores are to be handled. Other modifications in the topology to maintain modularity and improve transient response are being investigated.
This research is supported by Strategic Research Initiative, Engineering at Illinois.