PhD student Dipanjan Das with advisor P. Krein
Power delivery to multi-core processors continues to be challenging as transistor sizes and their operating voltages decrease. While core numbers in each processor increase, power requirements remain the same with each new microprocessor generation, and handling transient performance requirements along with efficiency is especially difficult at lower voltages. Significant improvement in energy efficiency can be achieved by stacking the processor cores in series and regulating the core voltages by differential power processing (DPP), since power delivery is possible at a higher voltage (lower current). However, for practically achieving higher efficiency than the conventional parallel-connected processor core architecture, other (software) overheads are required to balance the power consumption of each processor core (such as communication between different voltage domains, scheduling processes to aid voltage balancing, etc.).
Control schemes to improve DPP voltage regulator dynamics include the hierarchical element-to-element topology, which provides improved dynamic performance compared to other non-isolated topologies in regulating stack voltages. Implementation of the bidirectional DPP converters has been one focus. A bidirectional multi-phase buck/buck-boost converter with asymmetric current sharing (see Figure 1) was developed to improve efficiency over a wide load range, and a load range of over 100x has been demonstrated.
Lower losses in individual DPP converters at light load are expected to significantly improve system-level efficiencies. A series stack of eight low-voltage high-current loads with DPP voltage regulators is under development for validation of the claimed advantages of the series-connected system over the conventional parallel power delivery system. The series stack will be supplied directly from a 48V bus through a two-phase buck converter. This research is supported by the Grainger Center for Electric Machinery and Electromechanics.