Dipanjan Das with adviser P. Krein
Power delivery to multi-core processors is challenging. Decreasing transistor sizes lead to decreasing operating voltages. Core numbers in each processor are increasing, while power requirements tend to remain the same. Thus, handling processor output impedance as supply voltages are reduced is becoming progressively more difficult.  Significant improvement in energy efficiency can be achieved by stacking the cores in series (thereby increasing the output voltage requirement and relaxing the output impedance requirement for the outer loop converter) and regulating the core voltages by differential power processing (DPP).

The element-to-element DPP configuration seems to be most appropriate for our purpose because of its modularity and ease of integration due to lower switch voltages compared to other possible topologies. However, for the conventional load-to-load architecture of back-to-back connected buck-boost converters, the dynamic response is demanding due to the coupled nature of the architecture. A large number of these converters cannot be connected back to back if the goal is fast transient response. Modified topologies derived from the load-to-load DPP topology are being analyzed. Developed hardware shown in Figure 27 was tested to deliver 50W of power to a series stack of four voltage domains at 98 percent efficiency under 10 percent current mismatch between loads. A control for improving converter efficiency at light load by going into discontinuous modes is being developed and is expected to further improve system efficiency. This research is supported in part by the by Strategic Research Initiative program, Engineering at Illinois.


Figure 27: PCB for supplying four series-connected digital domains (4”x 4”)