Thomas Foulkes with advisers Prof. Nenad Miljkovic and Prof. Robert Pilawa-Podgurski
Designing and optimizing high frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide-bandgap transistors have enabled simultaneous expansion in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistance, and reduced parasitic inductances and capacitances.
The early acceptance of gallium-nitride (GaN) transistors was plagued by detrimental dynamic on-state resistance effects. This non-linear, second-order phenomenon for GaN devices is characterized by an increase in on-state resistance with rising voltage and temperature stress. While device manufacturers have made significant improvements compared to early-generation devices, experimental evidence for a survey of commercial GaN transistors shows that a significant build-up in on-state resistance with voltage and temperature stress still exists. This new method for measuring dynamic on-state resistance has promise for shedding light on the dynamic on-state resistance limitations of GaN devices due to the independent control of drain current, voltage stress, pulse-width for device conduction time, and package temperature. Based on a survey of low-voltage GaN transistors, metrics were proposed to quantify the dynamic on-state resistance performance of a specific device and facilitate a fair comparison between different GaN device technologies, as shown in Figure 1. This research is supported by an NSF Graduate Research Fellowship, NASA, and POETS.