PhD student Christopher Barth with advisor R. Pilawa-Podgurski

Funding Source: NASA motor and inverter project


Figure 18: FPGA master and slave configuration

Flying capacitor multilevel inverter (FCML) topology has been shown to enable high power density and efficiency. In order to ensure maximum efficiency and reliability, it is advantageous to power large loads by operating many inverters in parallel. This provides redundancy in the case of a failure and allows the number of inverters running to be reduced so those remaining are operated near their peak efficiency.


Such a parallel configuration necessitates coordinated control of the multiple inverters. The complexity of the FCML structure and the number of pulse-width modulated signals needed for driving switches requires that each inverter contain local pulse-width modulation generation and minimal control. System control, therefore, requires coordinated control of these local inverters by a global control system. This is shown in “FPGA Master (field-programmable gate array) and Slave Configuration.”  in figure 18. With coordinated global control, individual FCML inverters can be stacked to form a completed inverter as shown in Figure 19. Ongoing work, funded by NASA is focused on developing current mode control of the inverter system. After developing the initial control strategy, additional research will be done to improve system fault tolerance and control bandwidth.


Figure19: FCML inverters stacked to form a completed inverter