Roy Bell with adviser R. C. N. Pilawa-Podgurski
This work seeks to replace state-of-the-art power electronic solutions for the MPPT of
PV sub-modules with an architecture that facilitates the use of inexpensive, module-integrable, and efficient power electronics. The topology of Fig. 18, known as the dc optimizer, is commonly implemented to extract maximum power from a PV installation and requires each power converter to process the full power of its corresponding PV sub-module. This necessitates highly rated components, increases both size and cost of the power converters, and constrains improvements in converter efficiency. Furthermore, system-level efficiency is limited by converter efficiency, as the total generated power is processed by all the converters.
Differential power processing solves the problems of a topology like the dc optimizer in Fig. 18(a). A variation of DPP illustrated in Fig. 18(b) is referred to as the element-to-virtual bus DPP architecture. For non-uniform insolation across PV sub-modules, the generated photo-current of each sub-module varies in magnitude between sub-modules, and thus, the current corresponding to the maximum power point of a sub-module will differ from sub-module to sub-module. The role of the DPP converters in Fig. 18(b) is to inject or absorb the difference in current necessary to operate its sub-module at its MPP. Variation in insolation across sub-modules is typically small, so the current and, thus, power processed is significantly lower than that of the dc optimizer. This allows selection of converters with lower rated components, yielding a design that is less expensive and more integrable than that used in the dc optimizer topology. In addition, the implementation of isolated dc-to-dc converters enables arbitrary selection of the parallel output voltage in Fig. 18(b), which may result in a balanced isolated dc-to-dc converter design. Harmonic and proximity factors associated with power loss in the converter magnetic components are reduced. The parallel output also greatly facilitates communication between all converters.
Figure 18 also presents a comparison between the power processed in the dc optimizer configuration and the power processed in the element-to-virtual bus architecture. The MPP of sub-modules 1, 2, and 3 are 36 W, 60 W, and 60 W, respectively. The MPP voltage of each sub-module is 12 V. Maximum possible power generated is the sum of the sub-module MPP’s—156 W. For comparison, the efficiency of all converters is 95%. Figure 18 shows that the DPP architecture processes less power, resulting in 78.6% less power loss than the dc optimizer topology.
This work was supported by the Grainger Center for Electric Machinery and Electromechanics, Advanced Research Projects Agency-Energy (ARPA-E), and U.S. Department of Energy Award Number DE-AR0000217.